1. Field of the Invention
This application is related to the field of integrated circuit design methodology and tools, and more particularly to transistor level simulation.
2. Description of the Related Art
One design specification that must be met in many integrated circuit designs is a lifetime requirement. That is, a typical instance of the integrated circuit must be able to operate for at least a certain designated period of time. A factor that influences the lifetime of the integrated circuits is the aging of transistors that are included in the integrated circuits.
Over time, transistors in the integrated circuit can experience various aging effects such as Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), etc. BTI can include negative BTI (NBTI) for P-type metal-oxide-semiconductor (PMOS) transistors and positive BTI (PBTI) for and n-type MOS (NMOS) transistors. The aging effects change the operation of the transistors, typically reducing their performance. For example, the magnitude of the saturation current in the transistor can decrease, the threshold voltage required to activate the transistor can increase, etc. Accordingly, the operational characteristics of the circuit (e.g. its timing or power consumption) can change over time. Eventually, these changes result in the integrated circuit becoming non-functional or subject to erroneous operation.
One mechanism for increasing the lifetime of the integrated circuit is to simulate the aging effects that can be experienced in the integrated circuit, and to design the circuitry to continue to function properly in the presence of aged transistors. That is, the circuit can be designed to tolerate up to a certain amount of aging effects while still remaining within specification for the circuit, so that the integrated circuit still functions properly.
Various commercially-available software tools can be used to model aging effects. Typically, these tools use transistor models provided by the foundries that manufacture integrated circuits. The foundries typically provide models for one type of simulator (e.g. the Spectre Simulator, from Cadence Design Systems, Inc. (San Jose, Calif.)) and have not validated models for other simulators such as SPICE-based simulators. Accordingly, the models provided by the foundries are expressed using syntax defined by the simulator selected by the foundry. Some simulators also have a limitation on the size of the circuit design that they can simulate, which in turn limits the size of the circuit to which the aging tools can be applied. For example, large cache and/or memory arrays often cannot be processed by such tools. A design house that wishes to simulate large models and/or use a different model (e.g. from a different foundry) is prevented from doing so.